1. Technical Field
The present invention generally relates to electronic circuits and in particular to receivers for data communication systems. Still more particularly, the present invention relates to the on-chip diagnostic of receiver systems while operating in functional mode.
2. Description of the Related Art
High bandwidth chip-to-chip interconnection is a crucial part of many of today's digital communication systems. High speed input/output (I/Os) are extensively used in server processors, memory to central processing unit (CPU) interfaces, multiprocessor systems, and gaming applications. These I/Os which are part of the physical layer of a data communication system are designed to operate at a given Bit Error Rate (BER) with some predefined margins. These predefined margins are the vertical and horizontal eye openings of the received data as seen by the decision circuit of the receiver at the given BER. The margin is usually verified by mathematically modeling a link or by experimentation in the laboratory. Taking into account all the variability of all the link components, i.e. the electronic circuits, the transmission medium, external perturbation and other distortion and attenuation factors, the process of verifying the margins becomes very difficult and tedious.
The vertical eye opening is readily measured on-chip by utilizing an additional decision circuit having a pre-defined input voltage offset that matches the needed margin. The result of the decision circuit is then compared to that of the circuit processing the functional data. The additional cost of such an-chip diagnostic is minimal. However, checking the horizontal eye opening on-chip is difficult and usually incurs a penalty in power consumption and increased on-chip real estate. This difficulty and corresponding penalty is especially evident for receiver systems that use two (2) samples per symbol (known as 2× over sampling receivers) of the received data to extract the timing information and sample the data.